|Summary |Design Structures |Sequential Statements |Concurrent Statements |Types and Constants |
|Declarations |Delay, Events |Reserved Words |Operators |System Tasks |Compiler Directives |
The type names below are automatically defined. The types are reserved words thus you can not re-define them. Users can augment predefied type with modifiers, vectors and arrays. See Verilog Declarations for how to declare identifiers.
Beware of automatic type conversion. You may get a surprise. The value set for Verilog is: 0 - represents number zero, logic zero, logical false 1 - represents number one, logic one, logical true x - represents an unknown logic value z - represents high impedance logic value most data types can store all four values.
There are two groups of types, "net data types" and "variable data types." An identifier of "net data type" means that it must be driven. The value changes when the driver changes value. These identifiers basically represent wires and are used to connect components. "net data types" are: wire, supply0, supply1, tri, triand, trior, tri0, tri1, wand, wor "net data types" can have strength modifiers: supply0, supply1, strong0, strong1, pull0, pull1, weak0, weak1, highz0, highz1, small, medium, large. some "net data types" can take modifiers: signed, vectored, scalared.
There are two groups of types, "net data types" and "variable data types."
An identifier of "variable data type" means that it changes value upon
assignment and holds its value until another assignment. This is a
traditional programming language variable and is used in sequential
statements.
"variable data types" are: integer, real, realtime, reg, time.
integer is typically a 32 bit twos complement integer.
real is typically a 64 bit IEEE floating point number.
realtime is of type real used for storing time as
a floating point value.
reg is by default a one bit unsigned value.
The reg variable data type may have a modifier signed,
and may have may bits by using the vector modifier [msb:lsb].
time is typically 64 bit unsigned value that is the simulation time
The system function $time provides the simulation time.
integer 3 123456 -7
real 1.0 0.1 123e-5 123.0E-5 -5.2 per IEEE 754-1985
typically 64 bit
string "a string" constant string, no extra characters, no terminator,
may be stored into almost any type.
There is no type 'char' or 'string'.
specifying radix and special values
The general structure is: width´radix value
width is integer, automatic extension to 16 bits
radix is d or D for integer (optional)
h or H for hexadecimal
o or O for octal
b or B for bit
examples:
´h ff is 00ff hex // default 16 bit
16´h ff is 00ff hex
1´b 1 or just 1
1´b 0 or just 0
1´b x needed for x unknown (not just 'x')
1´b z needed for z high impedance
32´H 0XZ1FABX hexadecimal 32 bits in four bit groups
8´B 0110_1100 binary 01101100 8-bits
4´b 10xz four bits 10XZ
18´o 777777 octal, 18 bits of ones
7´d 123 just decimal 123 with length 7
Vectors are are multiple bit types. The next section covers arrays
that create multiple entries including arrays of vectors.
The "net data types" and the one variable type reg are by
default one bit in length and by default unsigned.
wire will be used as representing all "net data types".
wire[31:0] is a vector type having 32 bits with the
most significant bit numbered 31 and the
least significant bit numbered zero. This
type denotes 32 wires.
A declaration:
wire[31:0] a; declares a to be 32 wires.
just 'a' is all 32 wires,
a[31] is the most significant bit
a[0] is the least significant bit
a[15:8] is eight wires, bits 15 to 8 of 'a'
wire[1:12] is a vector type having 12 bits with the
most significant bit numbered 1 and the
least significant bit numbered 12. This
type denotes 12 wires that can connect
components.
reg[-10:10] is a vector type having 21 bits with a
most significant bit -10 and a least
significant bit 10. This is a variable
that can be assigned values.
reg signed [7:0] is a vector type for values
from -128 to +127. In other words
two´s complement values.
Arrays apply to identifiers. Identifiers have a type as covered in
the previous section.
type identifier array-definition; is the form used to define an array.
integer a[1:10]; is a typical array of integers
a[1] is the first element, a[10] is the last element.
reg[31:0] mema[0:4095]; is a typical memory, 4096 words of 32 bits
per word.
mema[2] is the third word in memory
mema[2][31] is the most significant bit
of the third word in memory.
real matrix[1:20][1:20]; is a two dimensional array of real values.
access as matrix[i][j]
wire[7:0] vid_mem[1:3][799:0][599:0]; 3D organized bytes
access as vid_mem[rgb][horiz][vert]
to wire memory bytes to components.
Typically using the generate capability.
Restriction: You can not access an entire array. You can not access
a slice of an array. e.g. a[3:5] is illegal.