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Verilog Concurrent Statements

These statements are for use in ???.

Concurrent Statements

block statement

Used to group concurrent statements, possibly hierarchically.

  label : block [ ( guard expression ) ] [ is ]
             [ generic clause [ generic map aspect ; ] ]
             [ port clause [ port map aspect ; ] ]
             [ block declarative items ]
          begin
             concurrent statements
          end block [ label ] ;

  clump : block
          begin
            A <= B or C;
            D <= B and not C;
          end block clump ;

  maybe : block ( B´stable(5 ns) ) is
             port (A, B, C : inout std_logic );
             port map ( A => S1, B => S2, C => outp );
             constant delay: time := 2 ns;
             signal temp: std_logic;
          begin
             temp <= A xor B after delay;
             C <= temp nor B;
          end block maybe; 

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