Verilog-XL Command-Line Options

You can access information on the following Verilog-XL Version 2.7 features:

Verilog-XL Command-Line Options (this page)
Verilog-XL Command-Line Plus Options
Verilog-XL Compiler Directives
Verilog-XL System Tasks and Functions

Option Description

-a
(accelerate) Overrides the +noxl option and causes the XL algorithm (the default) to accelerate all possible elements of the source description.

-c
(compile only) Compiles the source text only and then exits. If you use the restart option (-r) with the -c option. Verilog-XL loads the data file but does not perform the simulation.

-d
(decompile) Prints out a decompilation of the generated data structure after the source text has been compiled and linked, or after a saved data file (see the -r option) has been loaded. This option is mainly for system testing purposes, but you can also use it to decompile a saved data file to find out what it contains, or to recreate a design for which the original source text has been lost.

-f <filename>
(command argument file) Instructs Verilog-XL to read the text file that you specify following the option. The text file can contain source text filenames and Verilog-XL command options, including other -f options. Nesting is virtually unlimited, but a maximum of 1024 characters has been set to trap recursive -f options.

-i <filename>
(input file) Allows interactive commands to be read from a file. At the end of this file, interactive commands can be read from the keyboard or other standard input. You must provide the filename following the -i option.

-k <filename>
(key file) Changes the default key filename (verilog.key) to the name you specify following the -k option. A key file contains standard input.

-l <filename>
(log file) Changes the default log filename (verilog.log) to the name you specify following the -l option. A log file contains standard output.

-q
(quiet) Suppresses the display of messages during the major steps in compilation and simulation.

-r <filename>
(restart) Restarts the simulator using a data file previously saved with the $save system task. Do not specify source text files on the command line with this option.

-s
(stop) Stops the simulator at time 0 after compilation and puts you in interactive mode. You can use the $stop system task in the source description instead of the -s stop option.

-t
(trace) Performs a full trace of all simulation events from the start of simulation (same trace as given by the $settrace system task).

-u
(uppercase) Converts all Verilog identifiers to uppercase (in the source code and in interactive mode) to verify that the source description does not rely on case sensitivity.

-v <filename>
(library file) Tags modules as cells in a library file. (See `celldefine for more information.) If the library contains hierarchies, the top module in each hierarchy is the cell.

-w
(warning suppression) Suppresses the display of messages that report inconsistencies in module port connections, such as when vector sizes are mismatched or not enough connections have been specified.

-x
(vector net expansion) Expands all vector nets, except those specified by compiler directives and keywords that control expansion.

-y <directoryname>
(library directory) Tags modules in a library directory as cells. (See `celldefine for more information.) If the library contains hierarchies, the top module in each hierarchy is the cell.

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Option	Description
-a (accelerate)	Overrides the +noxl option and causes the XL algorithm (the default) to accelerate all possible elements of the source description.
-c (compile only)	Compiles the source text only and then exits. If you use the restart option (-r) with the -c option. Verilog-XL loads the data file but does not perform the simulation.
-d (decompile)	Prints out a decompilation of the generated data structure after the source text has been compiled and linked, or after a saved data file (see the -r option) has been loaded. This option is mainly for system testing purposes, but you can also use it to decompile a saved data file to find out what it contains, or to recreate a design for which the original source text has been lost.
-f <filename> (command argument file)	Instructs Verilog-XL to read the text file that you specify following the option. The text file can contain source text filenames and Verilog-XL command options, including other -f options. Nesting is virtually unlimited, but a maximum of 1024 characters has been set to trap recursive -f options.
-i <filename> (input file)	Allows interactive commands to be read from a file. At the end of this file, interactive commands can be read from the keyboard or other standard input. You must provide the filename following the -i option.
-k <filename> (key file)	Changes the default key filename (verilog.key) to the name you specify following the -k option. A key file contains standard input.
-l <filename> (log file)	Changes the default log filename (verilog.log) to the name you specify following the -l option. A log file contains standard output.
-q (quiet)	Suppresses the display of messages during the major steps in compilation and simulation.
-r <filename> (restart)	Restarts the simulator using a data file previously saved with the $save system task. Do not specify source text files on the command line with this option.
-s (stop)	Stops the simulator at time 0 after compilation and puts you in interactive mode. You can use the $stop system task in the source description instead of the -s stop option.
-t (trace)	Performs a full trace of all simulation events from the start of simulation (same trace as given by the $settrace system task).
-u (uppercase)	Converts all Verilog identifiers to uppercase (in the source code and in interactive mode) to verify that the source description does not rely on case sensitivity.
-v <filename> (library file)	Tags modules as cells in a library file. (See `celldefine for more information.) If the library contains hierarchies, the top module in each hierarchy is the cell.
-w (warning suppression)	Suppresses the display of messages that report inconsistencies in module port connections, such as when vector sizes are mismatched or not enough connections have been specified.
-x (vector net expansion)	Expands all vector nets, except those specified by compiler directives and keywords that control expansion.
-y <directoryname> (library directory)	Tags modules in a library directory as cells. (See `celldefine for more information.) If the library contains hierarchies, the top module in each hierarchy is the cell.