VHDL Sequential Statements

These statements are for use in Processes, Procedures and Functions.
The signal assignment statement has unique properties when used sequentially.

Sequential Statements

wait statement

Cause execution of sequential statements to wait.

 [ label: ] wait [ sensitivity clause ] [ condition clause ] ;

 wait for 10 ns;              -- timeout clause, specific time delay.
 wait until clk='1';          -- condition clause, Boolean condition
 wait until A>B and S1 or S2; -- condition clause, Boolean condition
 wait on sig1, sig2;          -- sensitivity clause, any event on any
                              -- signal terminates wait

assertion statement

Used for internal consistency check or error message generation.

 [ label: ] assert boolean_condition [ report string ] [ severity name ] ;

 assert a=(b or c);
 assert j<i report "internal error, tell someone";
 assert clk='1' report "clock not up" severity WARNING;

 predefined severity names are: NOTE, WARNING, ERROR, FAILURE
 default severity for assert is ERROR

report statement

Used to output messages.

 [ label: ] report string [ severity name ] ;

 report  "finished pass1";  -- default severity name is NOTE
 report  "Inconsistent data." severity FAILURE;

signal assignment statement

The signal assignment statement is typically considered a concurrent
statement rather than a sequential statement. It can be used as
a sequential statement but has the side effect of obeying the
general rules for when the target actually gets updated.

In particular, a signal can not be declared within a process or
subprogram but must be declared is some other appropriate scope.
Thus the target is updated in the scope where the target is declared
when the sequential code reaches its end or encounters a 'wait'
or other event that triggers the update.

 [ label: ] target <= [ delay_mechanism ] waveform ;

  delay_mechanism
    transport
    reject time_expression
    inertial

  waveform
    waveform_element [, waveform_element]
    unaffected
 
  waveform_element
    value_expression [ after time_expression ]
    null [ after time_expression ]


  sig1 <= sig2;
  Sig <= Sa and Sb or Sc nand Sd nor Se xor Sf xnor Sg;
  sig1 <= sig2 after 10 ns;
  clk <= '1' , '0' after TimePeriod/2 ; 
  sig3 <= transport sig4 after 3 ns;
  sig4 <= reject 2 ns sig5 after 3 ns; -- increasing time order
  sig6 <= inertial '1' after 2 ns, '0' after 3 ns , '1' after 7 ns;

  Note: omitting  [ after time_expression ] is equivalent
        to after 0 fs;

 More information in Concurrent Statements signal assignment statement.

variable assignment statement

Assign the value of an expression to a target variable.

 [ label: ] target := expression ;

 A := -B + C * D / E mod F rem G abs H;
 Sig := Sa and Sb or Sc nand Sd nor Se xor Sf xnor Sg;

procedure call statement

Call a procedure.

 [ label: ] procedure-name [ ( actual parameters ) ] ;

 do_it;  -- no actual parameters

 compute(stuff, A=>a, B=>c+d); -- positional association first,
                                     -- then named association of
                               -- formal parameters to actual parameters

if statement

Conditional structure.

 [ label: ] if  condition1  then
                 sequence-of-statements
            elsif  condition2  then      \_ optional
                 sequence-of-statements  /
            elsif  condition3  then      \_ optional
                 sequence-of-statements  /
            ...

            else                         \_ optional
                 sequence-of-statements  /
            end if [ label ] ;

 if a=b then
     c:=a;
 elsif b<c then
     d:=b;
     b:=c;
 else
     do_it;
 end if;

case statement

Execute one specific case of an expression equal to a choice.
The choices must be constants of the same discrete type as the expression.

 [ label: ] case  expression  is
              when choice1 =>
                 sequence-of-statements
              when choice2 =>            \_ optional
                 sequence-of-statements  /
              ...

              when others =>             \_ optional if all choices covered
                 sequence-of-statements  /
            end case [ label ] ;

  case  my_val  is
    when 1 =>
      a:=b;
    when 3 =>
      c:=d;
      do_it;
    when others =>
      null;
  end case;

loop statement

Three kinds of iteration statements.

 [ label: ] loop
                 sequence-of-statements -- use exit statement to get out
            end loop [ label ] ;

 [ label: ] for variable in range loop
                 sequence-of-statements
            end loop [ label ] ;

 [ label: ] while  condition  loop
                 sequence-of-statements
            end loop [ label ] ;

  loop
    input_something;
    exit when end_file;
  end loop;

  for I in 1 to 10 loop
    AA(I) := 0;
  end loop;

  while not end_file loop
    input_something;
  end loop;


all kinds of the loops may contain the 'next' and 'exit' statements.

next statement

A statement that may be used in a loop to cause the next iteration.

 [ label: ] next [ label2 ] [ when condition ] ;

 next;
 next outer_loop;
 next when A>B;
 next this_loop when C=D or done; -- done is a Boolean variable

exit statement

A statement that may be used in a loop to immediately exit the loop.

 [ label: ] exit [ label2 ] [ when condition ] ;

 exit;
 exit outer_loop;
 exit when A>B;
 exit this_loop when C=D or done; -- done is a Boolean variable

return statement

Required statement in a function, optional in a procedure.

 [ label: ] return [ expression ] ;

 return; -- from somewhere in a procedure
 return a+b; -- returned value in a function

null statement

Used when a statement is needed but there is nothing to do.

 [ label: ] null ;

 null;