# Makefile for Cadence VHDL BE CAREFUL, in samples/ *.out edited neutral
#
# use  tcsh
#      source vhdl_cshrc
#      make
#
# must have set up  cds.lib  and  hdl.var  in default directory
# must have initialized library  WORK  and have  hdl.var point to it.

all: bmul32_test.out  div_ser.out      mul_ser_g.out    stall_down.out  \
     bmul_ser.out     sqrt32.out       stall_up.out                     \
     ctest1.out       mul32c_test.out  sqrt8.out        test_bshift.out \
     ctest1a.out      mul_ser.out      sqrt8m.out       test_g.out


hello_world.out: hello_world.vhdl
	ncvhdl -v93 hello_world.vhdl
	ncelab -v93 hello_world:test
	ncsim -batch -logfile hello_world.out -input hello_world.run hello_world

hello_proc.out: hello_proc.vhdl
	ncvhdl -v93 hello_proc.vhdl
	ncelab -v93 hello_proc:test
	ncsim -batch -logfile hello_proc.out -input hello_proc.run hello_proc

t_table.out: t_table.vhdl
	ncvhdl -v93 t_table.vhdl
	ncelab -v93 t_table:test
	ncsim -batch -logfile t_table.out -input t_table.run t_table

file_io.out: file_io.vhdl
	ncvhdl -v93 file_io.vhdl
	ncelab -v93 file_io:test
	ncsim -batch -logfile file_io.log -input file_io.run file_io

add32_test.out: add32.vhdl add32_test.vhdl add32_test.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 add32_test.vhdl
	ncelab -v93 add32_test:circuits
	ncsim -batch -logfile add32_test.out -input add32_test.run add32_test

tadd32.out: add32.vhdl tadd32.vhdl tadd32.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 tadd32.vhdl
	ncelab -v93 tadd32:circuits
	ncsim -batch -logfile tadd32.out -input tadd32.run tadd32

add32_test_pg.out: add32pg.vhdl add32_test.vhdl add32_test.run
	ncvhdl -v93 add32pg.vhdl
	ncvhdl -v93 add32_test_pg.vhdl
	ncelab -v93 add32_test_pg:circuits
	ncsim -batch -logfile add32_test_pg.out -input add32_test.run add32_test_pg

add32_test_b.out: add32_test_pg.vhdl add32pg.vhdl add32_test.run
	ncvhdl -v93 add32pg.vhdl
	ncvhdl -v93 add32_test_b.vhdl
	ncelab -v93 add32_test_b:circuits
	ncsim -batch -logfile add32_test_b.out -input add32_test.run add32_test_b

test_bshift.out: test_bshift.vhdl test_bshift.run
	ncvhdl -v93 test_bshift.vhdl
	ncelab -v93 bshift_config
	ncsim  -batch -logfile test_bshift.out -input test_bshift.run bshift_config

test_shared.out: test_shared.vhdl part1.asm part1.abs test_shared.run
	ncvhdl -v93 test_shared.vhdl
	ncelab -v93 test_shared:schematic
	ncsim  -batch -logfile test_shared.out -input test_shared.run test_shared

pipe1.out: pipe1.vhdl add32.vhdl pipe1.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 pipe1.vhdl
	ncelab -v93 pipe1:schematic
	ncsim  -batch -logfile pipe1.out -input pipe1.run pipe1

pipe1c.out: pipe1c.vhdl  pipe1c.run
	ncvhdl -v93 pipe1c.vhdl
	ncelab -v93 pipe1c_config
	ncsim  -batch -logfile pipe1c.out -input pipe1c.run pipe1c_config

pipe1_87.out: pipe1.vhd pipe1.run # VHDL 87
	ncvhdl  pipe1.vhd
	ncelab  pipe1_config
	ncsim  -batch -logfile pipe1_87.out -input pipe1.run pipe1_config

pipe2.out: pipe2.vhdl add32.vhdl pipe2.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 pipe2.vhdl
	ncelab -v93 pipe2:schematic
	ncsim  -batch -logfile pipe2.out -input pipe2.run pipe2

pipe2c.out: pipe2c.vhdl pipe2c.run
	ncvhdl -v93 pipe2c.vhdl
	ncelab -v93 pipe2c_config
	ncsim  -batch -logfile pipe2c.out -input pipe2c.run pipe2c_config

pipe2_87.out: pipe2.vhd pipe2.run # VHDL 87
	ncvhdl pipe2.vhd
	ncelab pipe2_config
	ncsim  -batch -logfile pipe2_87.out -input pipe2.run pipe2_config

part1_start.out: part1_start.vhdl add32.vhdl part1.asm part1.abs part1.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 part1_start.vhdl
	ncelab -v93 part1:schematic
	ncsim  -batch -logfile part1_start.out -input part1.run part1

part1c_start.out: part1c_start.vhdl part1c.asm part1c.abs part1c_start.run
	ncvhdl -v93 part1c_start.vhdl
	ncelab -v93 part1c_config
	ncsim  -batch -logfile part1c_start.out -input part1c.run part1c_config

part1.out: part1.vhdl add32.vhdl bshift.vhdl part1.asm part1.abs part1.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 bshift.vhdl
	ncvhdl -v93 part1.vhdl
	ncelab -v93 part1:schematic
	ncsim  -batch -logfile part1.out -input part1.run part1

part1c.out: part1c.vhdl part1c.asm part1c.abs part1c.run
	ncvhdl -v93 part1c.vhdl
	ncelab -v93 part1c_config
	ncsim  -batch -logfile part1c.out -input part1c.run part1c_config

part2a.out: part2a.vhdl add32.vhdl bshift.vhdl part2a.asm part2a.abs part2a.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 bshift.vhdl
	ncvhdl -v93 part2a.vhdl
	ncelab -v93 part2a:schematic
	ncsim  -batch -logfile part2a.out -input part2a.run part2a

part2ac.out: part2ac.vhdl part2ac.asm part2ac.abs part2ac.run
	ncvhdl -v93 part2ac.vhdl
	ncelab -v93 part2ac_config
	ncsim  -batch -logfile part2ac.out -input part2ac.run part2ac_config

part2b.out: part2b.vhdl add32.vhdl bshift.vhdl part2b.asm part2b.abs part2b.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 bshift.vhdl
	ncvhdl -v93 part2b.vhdl
	ncelab -v93 part2b:schematic
	ncsim  -batch -logfile part2b.out -input part2b.run part2b

part2bc.out: part2bc.vhdl part2bc.asm part2bc.abs part2bc.run
	ncvhdl -v93 part2bc.vhdl
	ncelab -v93 part2bc_config
	ncsim  -batch -logfile part2bc.out -input part2bc.run part2bc_config

part3a.out: part3a.vhdl add32.vhdl bshift.vhdl part3a.asm part3a.abs part3a.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 bshift.vhdl
	ncvhdl -v93 part3a.vhdl
	ncelab -v93 part3a:schematic
	ncsim  -batch -logfile part3a.out -input part3a.run part3a

part3b.out: part3b.vhdl add32.vhdl bshift.vhdl part3b.asm part3b.abs part3b.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 bshift.vhdl
	ncvhdl -v93 part3b.vhdl
	ncelab -v93 part3b:schematic
	ncsim  -batch -logfile part3b.out -input part3b.run part3b

test_g.out: test_g.vhdl add_g.vhdl reg_g.vhdl mux_g.vhdl cntr_g.vhdl test_g.run
	ncvhdl -v93 add_g.vhdl
	ncvhdl -v93 reg_g.vhdl
	ncvhdl -v93 mux_g.vhdl
	ncvhdl -v93 cntr_g.vhdl
	ncvhdl -v93 test_g.vhdl
	ncelab -v93 test_g:test
	ncsim  -batch -logfile test_g.out -input test_g.run test_g

mul_ser.out: mul_ser.vhdl add32.vhdl mul_ser.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 mul_ser.vhdl
	ncelab -v93 mul_ser:schematic
	ncsim  -batch -logfile mul_ser.out -input mul_ser.run mul_ser

bmul_ser.out: bmul_ser.vhdl add32.vhdl bmul_ser.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 bmul_ser.vhdl
	ncelab -v93 bmul_ser:schematic
	ncsim  -batch -logfile bmul_ser.out -input bmul_ser.run bmul_ser

mul_ser_r.out: mul_ser_r.vhdl add32.vhdl reg_32.vhdl mux_32.vhdl mul_ser_r.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 reg_32.vhdl
	ncvhdl -v93 mux_32.vhdl
	ncvhdl -v93 mul_ser_r.vhdl
	ncelab -v93 mul_ser_r:schematic
	ncsim  -batch -logfile mul_ser_r.out -input mul_ser_r.run mul_ser_r

mul_ser_g.out: mul_ser_g.vhdl add_g.vhdl reg_g.vhdl mux_g.vhdl cntr_g.vhdl \
               mul_ser_g.run
	ncvhdl -v93 add_g.vhdl
	ncvhdl -v93 reg_g.vhdl
	ncvhdl -v93 mux_g.vhdl
	ncvhdl -v93 cntr_g.vhdl
	ncvhdl -v93 mul_ser_g.vhdl
	ncelab -v93 mul_ser_g:schematic
	ncsim  -batch -logfile mul_ser_g.out -input mul_ser_g.run mul_ser_g

div_ser.out: div_ser.vhdl add32.vhdl div_ser.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 div_ser.vhdl
	ncelab -v93 div_ser:schematic
	ncsim  -batch -logfile div_ser.out -input div_ser.run div_ser

div_ser4.out: div_ser4.vhdl add32.vhdl div_ser4.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 div_ser4.vhdl
	ncelab -v93 div_ser4:schematic
	ncsim  -batch -logfile div_ser4.out -input div_ser4.run div_ser4

div_ser_g.out: div_ser_g.vhdl add_g.vhdl reg_g.vhdl mux_g.vhdl cntr_g.vhdl \
               div_ser_g.run
	ncvhdl -v93 add_g.vhdl
	ncvhdl -v93 reg_g.vhdl
	ncvhdl -v93 mux_g.vhdl
	ncvhdl -v93 cntr_g.vhdl
	ncvhdl -v93 div_ser_g.vhdl
	ncelab -v93 div_ser_g:schematic
	ncsim  -batch -logfile div_ser_g.out -input div_ser_g.run div_ser_g


mul_div_ser.out: mul_div_ser.vhdl add32.vhdl mul_div_ser.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 mul_div_ser.vhdl
	ncelab -v93 mul_div_ser:schematic
	ncsim  -batch -logfile mul_div_ser.out -input mul_div_ser.run mul_div_ser

jkff_cntr.out: jkff_cntr.vhdl jkff_cntr.run
	ncvhdl -v93 jkff_cntr.vhdl
	ncelab -v93 jkff_cntr:circuit
	ncsim  -batch -logfile jkff_cntr.out -input jkff_cntr.run jkff_cntr

jkffb_cntr.out: jkffb_cntr.vhdl jkffb_cntr.run
	ncvhdl -v93 jkffb_cntr.vhdl
	ncelab -v93 jkffb_cntr:circuit
	ncsim  -batch -logfile jkffb_cntr.out -input jkffb_cntr.run jkffb_cntr

dff_cntr.out: dff_cntr.vhdl dff_cntr.run
	ncvhdl -v93 dff_cntr.vhdl
	ncelab -v93 dff_cntr:circuit
	ncsim  -batch -logfile dff_cntr.out -input dff_cntr.run dff_cntr

dffb_cntr.out: dffb_cntr.vhdl dffb_cntr.run
	ncvhdl -v93 dffb_cntr.vhdl
	ncelab -v93 dffb_cntr:circuit
	ncsim  -batch -logfile dffb_cntr.out -input dffb_cntr.run dffb_cntr

test_attrib.out: test_attrib.vhdl test_attrib.run
	ncvhdl -v93 test_attrib.vhdl
	ncelab -v93 test_attrib:behavior
	ncsim  -batch -logfile test_attrib.out -input test_attrib.run test_attrib

mul32c_test.out: add32.vhdl mul32c.vhdl mul32c_test.vhdl mul32c_test.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 mul32c.vhdl
	ncvhdl -v93 mul32c_test.vhdl
	ncelab -v93 mul32c_test:circuits
	ncsim -batch -logfile mul32c_test.out -input mul32c_test.run mul32c_test

bmul32_test.out: add32.vhdl bmul32.vhdl bmul32_test.vhdl bmul32_test.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 bmul32.vhdl
	ncvhdl -v93 bmul32_test.vhdl
	ncelab -v93 bmul32_test:circuits
	ncsim -batch -logfile bmul32_test.out -input bmul32_test.run bmul32_test

div4r2_test.out: add32.vhdl div4r2_test.vhdl div4r2_test.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 div4r2_test.vhdl
	ncelab -v93 div4r2_test:test
	ncsim -batch -logfile div4r2_test.out -input div4r2_test.run div4r2_test

div8r2_test.out: add32.vhdl div8r2_test.vhdl div8r2_test.run
	ncvhdl -v93 add32.vhdl
	ncvhdl -v93 div8r2_test.vhdl
	ncelab -v93 div8r2_test:test
	ncsim -batch -logfile div8r2_test.out -input div8r2_test.run div8r2_test

divcsa_test.out: divcsa_test.vhdl csar2.vhdl csadiv.vhdl divcsa_test.run
	ncvhdl -v93 csar2.vhdl
	ncvhdl -v93 csadiv.vhdl
	ncvhdl -v93 divcsa_test.vhdl
	ncelab -v93 divcsa_test:test
	ncsim -batch -logfile divcsa_test.out -input divcsa_test.run divcsa_test

csa4r2.out: csa4r2.vhdl csa4r2.run
	ncvhdl -v93 csa4r2.vhdl
	ncelab -v93 mul4r2:schematic
	ncsim -batch -logfile csa4r2.out -input csa4r2.run mul4r2

ctest1.out:  ctest1.vhdl ctest1.run
	ncvhdl -v93 ctest1.vhdl
	ncelab -v93 add32_test:circuits
	ncsim -batch -logfile ctest1.out -input ctest1.run add32_test

ctest1a.out:  ctest1a.vhdl ctest1a.run
	ncvhdl -v93 ctest1a.vhdl
	ncelab -v93 ctest1a:circuits
	ncsim -batch -logfile ctest1a.out -input ctest1a.run ctest1a

stall_up.out:  stall_up.vhdl stall_up.run
	ncvhdl -v93 stall_up.vhdl
	ncelab -v93 stall_up:circuits
	ncsim -batch -logfile stall_up.out -input stall_up.run stall_up

stall_down.out:  stall_down.vhdl stall_down.run
	ncvhdl -v93 stall_down.vhdl
	ncelab -v93 stall_down:circuits
	ncsim -batch -logfile stall_down.out -input stall_down.run stall_down


mipsasm: mipsasm.cpp
	g++ -o mipsasm  mipsasm.cpp
	mipsasm test_mipsasm.asm test_mipsasm.abs

clean:
	rm -f junk*
	rm -f *~
	rm -f *.log
	rm -rf vhdl_lib
	mkdir  vhdl_lib
	chmod go+rx *
	chgrp cseeweb *

distribution:
	rm -f *.log
	rm -f *.tst
	rm -f *~
	rm -f *.bak
	rm -f junk*
	rm -rf vhdl_lib
	mkdir  vhdl_lib